1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of the Background Art
In response to the need for miniaturization and higher integration of semiconductor devices, great progress has been made in semiconductor micro-machining technology in recent years. This, in turn, has resulted in practical semiconductor devices having a multi-layer structure achieved by sequentially laminating a plurality of substrates upon which electrical elements are formed alternately with insulating layers. In such a semiconductor device having a multilayer structure, power is normally supplied to the individual electrical elements via through holes which are referred to as contact hole formed at the insulating layers. The contact hole is formed through etching and for this purpose an etching mask is formed through patterning on the front surface of a roughly planar insulating layer in the prior art.
In addition, when forming a pattern for contact holes that are too small to be formed through normal photolithography/etching processes, a method is adopted in which the side walls around the contact hole and areas other than the side walls are formed of polysilicon through separate steps to achieve an etching mask for contact hole formation in the prior art. This method in the prior art facilitates control of the bore diameter of the contact hole, which is achieved by varying the film thickness at the side walls only.
Furthermore, the method of the prior art described above, which uses an etching mask constituted of polysilicon, achieves an advantage in that the film thickness of the mask can be adjusted without affecting the resolution. In contrast, a conventional photoresist mask, which necessitates that the thickness of the photoresist be set to a large value to open deep contact hole since the selection ratio relative to the photoresist (the etching rate ratio of the photoresist/polysilicon) cannot be set large enough, presents problems such as a reduction in resolution occurring during the photolithography step due to the increase in the film thickness.
However, the method for manufacturing a semiconductor device in the prior art described above poses the following problems as the degree of integration and the film thickness of the insulating layers increase.
(1) Tapering of the contact hole shape caused by receding polysilicon side walls.
When the film thickness of an insulating layer increases, it naturally results in an increase in the length of time required for etching to form contact hole. In such a case, the polysilicon side wall portions are caused to recede by the etching process to increase the diameter at the upper portion of the contact hole. Consequently, the shape of the contact hole upper portion becomes tapered. If a wiring layer is present in the vicinity of a contact hole under these circumstances, the margin between the patterns is reduced by the increase in the diameter of the contact hole, and when the wiring layer to be connected to the contact hole is formed in a subsequent step, a shorting defect may occur between the wiring layer and the electrode provided at the contact hole.
(2) Shape defects caused by a higher aspect ratio.
While it is necessary to set the film thickness of the polysilicon pattern at a large value in order to avoid problems that would otherwise occur due to the tapering of the contact hole upper portion, the larger film thickness tends to induce phenomena such as bowing, whereby the diameter of the contact hole is caused to become larger in the middle and stoppage of the etching process at the middle portions of the contact hole due to the higher aspect ratio. In order to solve these problems, a high-density, low-pressure plasma must be generated, which necessitates installation of an expensive apparatus.
An object of the present invention, which has been completed by addressing the problems of the method for manufacturing a semiconductor device in the prior art discussed above, is to provide a new and improved semiconductor device and method for manufacturing a semiconductor device, through which shape defects at holes such as contact holes formed at an insulating layer can be prevented to reduce electrical defects such as shorting.
In order to achieve the object described above in a first aspect of the present invention, a method for manufacturing a semiconductor device that includes a hole formation process in which a hole is formed at an insulating layer laminated on a semiconductor substrate with the hole formation process comprising a step in which a preparatory hole having a diameter larger than the diameter of a hole that will reach a specific depth in the insulating layer is formed at a predetermined position at the insulating layer, a step in which a hole upper portion is formed by forming a protective wall having a specific thickness at the inner wall of the preparatory hole and a step in which a hole lower portion having a smaller diameter than the preparatory hole is formed at the bottom portion of the preparatory hole by using the protective wall as an etching mask.
In this method, the protective wall is employed as an etching mask during the formation of the lower portion of the hole. Since the protective wall is formed at the inner wall of the preparatory hole, the etching mask ultimately achieves a shape whereby it extends out over the insulating layer. As a result, by adopting this structure, advantages similar to those achieved when increasing the film thickness of the etching mask are achieved. Consequently, the degree to which the etching mask pattern becomes receded at the hole upper portion is reduced to prevent an increase in diameter at the hole upper portion.
In addition, in the structure described above in which the vertical portions of the etching mask that overhang toward the hole upper portion are large, the vertical hole shape can be maintained even when the etching time is extended due to an increase in the film thickness of the insulating layer without having to increase the thickness of the etching mask. Thus, when forming the hole through etching, the hole diameter does not become increased or the etching does not stop at the middle area of the hole.
Furthermore, since the upper portion of the hole is formed in advance, the lower portion of the hole can be formed through etching in practically the same way as when forming a shallower hole having roughly the same diameter. Moreover, since the formation of the preparatory hole can be implemented with a higher degree of accuracy compared to the formation of the hole itself, due to factors related to the aspect ratio, the upper portion of the hole can be formed with a high degree of accuracy. As a result, the formation accuracy of the hole overall is improved to further prevent occurrence of defects in the hole shape.
It is to be noted that a structure in which the protective walls in the structure described above remain unremoved may be adopted instead. Since such a structure in which the protective walls are not removed requires fewer manufacturing steps and is less time consuming compared to the structure in which the protective walls are removed, the cost of manufacturing the semiconductor device can be reduced.
For the formation of the preparatory hole in this method, a structure may be adopted in which an etching stop layer for inhibiting the progress of the etching in the depthwise direction of the preparatory hole is formed at a specific depth of the insulating layer. In this structure, over-etching is prevented by the presence of the etching stop layer to achieve reliable control of the depth of the preparatory hole, i.e., the height at which the protective walls overhang toward the insulating layer.
In addition, the formation of the preparatory hole may be achieved through a step in which a first layer and a second layer are sequentially laminated on an insulation layer, a step in which an initial preparatory hole reaching the insulating layer via the first layer and the second layer is formed on a predetermined preparatory hole formation position and a step in which a preparatory hole is formed at the insulating layer by simultaneously etching the second layer and the bottom portion of the initial preparatory hole until the first layer becomes exposed.
In the process described above, based upon the state in which the second layer is ground off to expose the first layer, etching end-point detection is achieved at the second layer and the bottom portion of the initial preparatory hole. For instance, if a dry etching method is adopted to etch the second layer and the bottom portion in the initial preparatory hole, the emission spectrum of the plasma generated by the etching process can be changed at the first layer and at the second layer. Thus, it becomes possible to detect the etching end point so that good control can be achieved over the depth of the preparatory hole, i.e., the height at which the protective walls overhang toward the insulating layer through prevention of over-etching.
As explained above, the method for manufacturing a semiconductor device according to the present invention realizes a stable and inexpensive semiconductor process technology to contribute to further miniaturization and higher integration of the semiconductor device.
In addition, in order to achieve the object described above, in a second aspect of the present invention, a semiconductor device comprising a semiconductor substrate, an insulating layer laminated on the semiconductor substrate and a hole formed at the insulating layer adopts a structure in which the hole is constituted of a hole upper portion constituted of a large diameter portion reaching a specific depth of the insulating layer and a hole lower portion constituted of a small diameter portion having a smaller diameter than the large diameter portion and located further toward the semiconductor substrate than the large diameter portion. The semiconductor device having this structure may be achieved through, for instance, the method in the first aspect of the present invention.
As explained above, through any of the methods for manufacturing a semiconductor device according to the present invention, the degree to which the etching mask pattern is caused to recede can by minimized and a vertical hole shape can be maintained. In addition, since the upper portion of the hole is formed in advance in any of the methods for manufacturing a semiconductor device according to the present invention, the etching of the insulating layer which would tend to induce defects in the hole shape can be performed in much the same manner as when forming a hole having a lower aspect ratio than that of the actual hole being formed. Thus, the structure in the second aspect of the present invention can be achieved through a manufacturing method that enables simple and highly accurate hole formation. As a result, a semiconductor device that is inexpensive and achieves further miniaturization and higher integration is provided.
It is to be noted that in the semiconductor device according to the present invention described above, the etching stop layer may be constituted of silicon nitride and that the insulating layer may be constituted of BPSG.